With tremendous growth of automotive and consumer market, demand of semiconductors is also growing. Every new day comes up with a new micro-controller with upgraded feature set. As the feature set is increasing, so is the complexity of the devices. This increased complexity majorly impacts the clocking and power sub system of a micro controller. In this paper, we will talk about clocking sub-system that is also known as HEART of any micro controller. To have a healthy heart of a micro controller, there should be robust testing of micro controller under various conditions. In a multiple clocking domain architecture, there are major issues of SoC getting stuck or wrong clock output. Sometimes, clock can get glitchy due to extreme weather conditions as well. It can also malfunction due to wrong configurations or a marginal configuration. So, to rule out all this kind of issues, randomization, sweeps, testing under different process, voltage and thermal conditions plays an important role. Though it is never possible to cover all the combinations during bench validation of these complex SoC, but in this paper, we have tried to capture some type of tests that can be performed to test the robustness of a micro controller.
| Published in | Automation, Control and Intelligent Systems (Volume 9, Issue 2) |
| DOI | 10.11648/j.acis.20210902.12 |
| Page(s) | 69-72 |
| Creative Commons |
This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited. |
| Copyright |
Copyright © The Author(s), 2024. Published by Science Publishing Group |
Clocking, Post-silicon, Validation, Stress Testing
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APA Style
Atulesh Kansal, Himanshu Aggarwal. (2021). Validating Clocking Subsystem in Post Silicon Environment. Automation, Control and Intelligent Systems, 9(2), 69-72. https://doi.org/10.11648/j.acis.20210902.12
ACS Style
Atulesh Kansal; Himanshu Aggarwal. Validating Clocking Subsystem in Post Silicon Environment. Autom. Control Intell. Syst. 2021, 9(2), 69-72. doi: 10.11648/j.acis.20210902.12
AMA Style
Atulesh Kansal, Himanshu Aggarwal. Validating Clocking Subsystem in Post Silicon Environment. Autom Control Intell Syst. 2021;9(2):69-72. doi: 10.11648/j.acis.20210902.12
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Download@article{10.11648/j.acis.20210902.12,
author = {Atulesh Kansal and Himanshu Aggarwal},
title = {Validating Clocking Subsystem in Post Silicon Environment},
journal = {Automation, Control and Intelligent Systems},
volume = {9},
number = {2},
pages = {69-72},
doi = {10.11648/j.acis.20210902.12},
url = {https://doi.org/10.11648/j.acis.20210902.12},
eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.acis.20210902.12},
abstract = {With tremendous growth of automotive and consumer market, demand of semiconductors is also growing. Every new day comes up with a new micro-controller with upgraded feature set. As the feature set is increasing, so is the complexity of the devices. This increased complexity majorly impacts the clocking and power sub system of a micro controller. In this paper, we will talk about clocking sub-system that is also known as HEART of any micro controller. To have a healthy heart of a micro controller, there should be robust testing of micro controller under various conditions. In a multiple clocking domain architecture, there are major issues of SoC getting stuck or wrong clock output. Sometimes, clock can get glitchy due to extreme weather conditions as well. It can also malfunction due to wrong configurations or a marginal configuration. So, to rule out all this kind of issues, randomization, sweeps, testing under different process, voltage and thermal conditions plays an important role. Though it is never possible to cover all the combinations during bench validation of these complex SoC, but in this paper, we have tried to capture some type of tests that can be performed to test the robustness of a micro controller.},
year = {2021}
}
TY - JOUR T1 - Validating Clocking Subsystem in Post Silicon Environment AU - Atulesh Kansal AU - Himanshu Aggarwal Y1 - 2021/07/13 PY - 2021 N1 - https://doi.org/10.11648/j.acis.20210902.12 DO - 10.11648/j.acis.20210902.12 T2 - Automation, Control and Intelligent Systems JF - Automation, Control and Intelligent Systems JO - Automation, Control and Intelligent Systems SP - 69 EP - 72 PB - Science Publishing Group SN - 2328-5591 UR - https://doi.org/10.11648/j.acis.20210902.12 AB - With tremendous growth of automotive and consumer market, demand of semiconductors is also growing. Every new day comes up with a new micro-controller with upgraded feature set. As the feature set is increasing, so is the complexity of the devices. This increased complexity majorly impacts the clocking and power sub system of a micro controller. In this paper, we will talk about clocking sub-system that is also known as HEART of any micro controller. To have a healthy heart of a micro controller, there should be robust testing of micro controller under various conditions. In a multiple clocking domain architecture, there are major issues of SoC getting stuck or wrong clock output. Sometimes, clock can get glitchy due to extreme weather conditions as well. It can also malfunction due to wrong configurations or a marginal configuration. So, to rule out all this kind of issues, randomization, sweeps, testing under different process, voltage and thermal conditions plays an important role. Though it is never possible to cover all the combinations during bench validation of these complex SoC, but in this paper, we have tried to capture some type of tests that can be performed to test the robustness of a micro controller. VL - 9 IS - 2 ER -
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